How to Build DPI Products? (Part I - CPU Architecture)

 

2 new documents, from Radisys and Netronome, may help DPI vendors to design high performance products. This post covers the latter, to be followed by the Radisys' document.

Nabil Damouny, senior director of business development at Netronome (a vendor of network flow processors), analyzes the CPU architecture for embedded communication equipment, such as DPI, and recommends the following:

"The combined solution is heterogeneous in nature: the x86 takes care of application processing, control plane processing and management, while the network flow processor manages the packet- and flow-based network I/O subsystem."   

See "The World of Secure, Virtualized Networking" - here.

"In a high-performance communication system, more than one type of processor is needed to keep up with the stringent requirements of packet processing, security and virtualization, especially at 10 Gbps and above. A typical communication system needs to be able to process packets and/or flows at all layers of the 7-Layer OSI model. x86 CPUs are an excellent choice for the application layer (L7) and control plane processing (see chart below)"  

"Highly programmable network flow coprocessors designed to work closely with commodity x86-based systems is a perfect match for security appliances (see chart below)."

See also -

• 
  
  Rumors: Cavium Received Proposal from Cisco - What does it Mean for DPI vendors?  - here
• 
  
  DPI Announcements - NetLogic 40Gbps Layer 7 Processing Solution  - here
• 
  
  DPI Announcements - Cavium Networks OCTEON II CN68XX  - here