EZchip Unveiled 400-Gb wire-speed, C-Programmable, NPU

EZchip unveiled the ".. NPS – Network Processor for Smart networks .. through its breakthrough architecture, NPS breaks the barriers imposed by traditional NPUs and CPUs. It enables extremely high-performance C-programmable layer 2-7 processing, and provides networking vendors with an architecture that scales as more advanced services at higher speeds are required over time".

"..Central to the NPS are its innovative CTOPs (C-programmable Task Optimized Processors). These processing engines build on EZchip’s extensive NPU experience and are designed specifically for data-plane processing. The optimized design allows the integration of 256 such processors, each with 16 threads, for a total of 4K virtual processing engines .. The NPS’ efficient design allows incorporating into the chip not only a great number of cores but also EZchip’s market-proven hardware traffic manager, a task optimized memory architecture, and numerous hardware accelerators for efficient table lookups, application recognition and security. The end result is a very powerful network processor with superior power efficiency and integration".

"The NPS provides great packet processing simplicity and flexibility through C-based programming, a standard toolset, support of the Linux® operating system, large code space, and a run-to-completion or pipeline programming style .. The NPS features cores that are highly optimized for packet processing and leverage EZchip’s vast packet processing and applications experience, a market-proven traffic manager, hardware accelerators for security and DPI (Deep Packet Inspection) tailored for efficiency and performance, on-chip search engines including TCAM with scaling through algorithmic extension to external low-cost low-power DRAM memory, a fabric adaptor to enable direct connection to a chassis backplane and switch fabric, and a multitude of interfaces providing an aggregated bandwidth of 800-Gigabits per second including 10-, 40- and 100-Gigabit Ethernet, Interlaken and PCI Express interfaces".

See "EZchip Introduces NPS, a New Breed of C-Programmable NPU that Enables the Next Wave of High-Performance Smart Carrier and Data-Center Networks" - here.